The present invention relates to a low power electronic device.
Advances in technology have allowed ever increasing functional products that cost less. Due to the increasing functionality, power consumption for each device has also increased. For certain products such as laptop or notebook computers, handheld computers, cellular telephones, and other wireless personal digital assistants that are designed for situations where power outlets are not available, the conservation of power is particularly important.
While portability requires compact, highly integrated devices to decrease size and weight, portable devices are not necessarily simplistic devices. For example, to handle wireless signal processing, cell phones and wireless handheld devices require intensive calculation and processing. One way to achieve high performance is to apply parallelism in the processing of instructions. For example, multiple execution units can be operated in parallel under the control of a dispatcher to permit simultaneous processing of instructions. While the use of multiple parallel-operated execution units increases the performance of the computer, this results in increased power consumption. Even though multiple parallel execution units increase the performance of the processor, power is wasted when some of the execution units are idle or performing no operations during various time intervals.
Designers have used various techniques for reducing power consumption of the processor. For example, as discussed in U.S. Pat. No. 6,088,807 to Maher, et al., the speed of the system clock is reduced to a fraction of the normal operating frequency during periods of inactivity. Since the power consumption of the processor is proportional to the frequency, reducing the frequency of the system clock also reduces the power consumption of the microprocessor. A second technique for reducing power turns off the system clock during periods of inactivity. Turning off the system clock affects all circuitry on the motherboard. Consequently, the circuitry that disables the system clock must also save all pertinent information in the microprocessor and associated board logic and restore the data upon resumption of activity such that the state of the computer after resumption of the system clock will be identical to the state of the computer prior to disabling the system clock. As a result, this technique for consuming power is both costly because of the complicated circuitry and slow because of the need to store and restore the state of the computer.
In clocked synchronous digital systems, a typical design style revolves around a single clock rate that drives all clocked elements of the design. Power is managed by turning on or off the clock to subsets of the system. Alternatively power may also be managed by slowing down the clock to a fraction of its normally active rate. For example, the Oak DSP features a “slow mode” whereby a DSP core may be software configured to divide its input clock by an integer N. The Oak processor is described at www.dspg.com/prodtech/core/teak.htm.
More recently, designs may rely on dynamic voltage management in order to reduce power consumption as in the Intel Xscale architecture; this however cannot be performed instantly and is targeted at relatively infrequent mode or usage changes. In one implementation of the Intel Xscale for mobile processing applications, the Intel 80200 processor, a single processor core, accepts an input clock frequency of 33 to 66 MHz and uses an internal PLL to lock to the input clock and multiplies the frequency by a variable multiplier to produce a high-speed core clock. This multiplier is initially configured by the PLL configuration pin and can be changed anytime later by software. Software has the ability to change the frequency of the clock without having to reset the core. Changing the clock frequency is similar to entering a low power mode. First, the core is stalled waiting for all processing to complete, second the new configuration is programmed, and then finally the core waits for the PLL to re-lock. This feature allows software to conserve power by matching the core frequency to the current workload.